The present invention relates to a refresh control system for a memory of the volatile type in a data processing system.
In a data processing system, a main memory is generally accessed by plural processing units through a memory bus. A volatile memory, such as a memory of MOS type, can be used as the main memory in the data processing system. In a MOS type memory element, the memory operation is performed by regarding the stored information as a logical value "1" or "0" in response to whether or not the stray capacitor between the gate and the substrate thereof is charged. However, in such a memory element, the charge of the stray capacitor tends to leak away and the information stored is lost with the lapse of time. Therefore, in order to maintain the stored information, it is required to periodically refresh the stored information in accordance with a predetermined cycle.
In a prior art refresh control system for accomplishing such a refresh operation, the refresh operation and accessing operation are selectively initiated in response to initiation signals for refresh and access. In such a system, since the initiation signal for refresh is asynchronous with the initiation signal for access, there is provided a flip-flop for synchronizing these signals. Since the output of the flip-flop is unstable during a period when the rising time of the refresh initiation signal is near to the rising time of the accessing initiation signal, the initiation of the operations must be delayed until the time when the output of the flip-flop becomes stable. Therefore, a long time is necessary for accessing of the main memory.
In order to avoid such a disadvantage, it is possible to synchronize the accessing initiation signal with the refresh initiation signal by transferring clock signals from the processing unit to the main memory. However, such a system has disadvantages in that the number of interface signal lines between the processing unit and the main memory are increased and the signals of the plural processing units must be synchronized with the signals of the main memory in a system in which the main memory is accessed by plural processing units.
On the other hand, a system can be realized in which the processing unit is interrupted by the refresh request and the refresh operation is executed after getting clearance for the interruption. However, such a system has disadvantages in that the number of interface signal lines is increased for interruption between the processing unit and the main memory unit and it is required to provide a control circuit for the interruption in the processing unit.